Optical Interconnect Bottlenecks: Optical Chips, DSPs & CPO Packaging

Disclaimer: This post reflects only my personal thinking and review of public industry materials and business logic. It does not constitute investment advice, and it does not involve any individual stock recommendations or implied positions. Markets carry risk; make your own independent decisions.

I read an industry write-up titled *US-Listed Optical Transceiver Full Industry Chain Analysis* (*《美股光模块全产业链解析来了！》*). Networking bottlenecks in AI data centers cannot be lumped under a vague claim that "optical modules benefit." I break the chain down into three layers: optical chips, DSP electrical chips, and packaging and assembly, plus the evolution toward CPO. Supply constraints, profit capture, business concentration, and cycle positioning differ at each layer.

This piece breaks optical modules into distinct links that can be checked separately, which is much more useful than simply repeating a sector slogan. Specifically, InP optical transmitter chips determine single-channel speed and cost, DSPs determine high-speed signal processing capability, and optical chips, first-level packaging, second-level packaging, and module manufacturing each take different slices of value. In the next stage with CPO, the industry pulls the optical engine closer to the switch chip or electrical chip to cut power consumption, latency, and signal loss. Reading through it, I will keep the sector name on my radar, but I am discounting the blanket "optical modules benefit" narrative upfront.

What Gets Stuck Changes Once Bandwidth Scales

The larger an AI cluster gets, the more important data movement between GPUs and servers becomes. Optical modules sit in the middle, converting between optical and electrical signals before sending data over fiber. As interconnect speeds move from 400G and 800G to 1.6T and 3.2T, the bottleneck goes beyond whether you can establish a link; it also depends on keeping power consumption, signal integrity, yield, and cost in check at higher bandwidths.

Optical Chips Bottleneck the Single Channel First

The write-up treats optical chips, especially optical transmitter chips, as the first choke point. High-end optical chips are often grown epitaxially on InP substrates, affecting single-channel speed, transmission distance, power consumption, and cost. While multi-channel parallelism can stack 100G / 200G single channels up to 800G / 1.6T, single-channel performance still dictates module efficiency and the subsequent upgrade path.

Optical chips do have technical barriers, though it is also easy to run into situations where a promising direction is already fully priced in. When looking at this layer, I look for concrete evidence: AI data center revenue share, customer concentration, order visibility, gross margin trends, and capital expenditure. The write-up did not provide these figures, so for now I only acknowledge the technical barrier, not that the profits have been realized.

DSPs Bottleneck the Signal

Once speeds reach 800G and 1.6T, loss, crosstalk, and distortion in the optical link increase noticeably, requiring a DSP to modulate, compensate, and clean up the signal. The material notes that a handful of electrical chip vendors hold a strong position in high-end optical module DSPs.

I agree that loss, crosstalk, and distortion will grow, which is why I do not look solely at the optical side; high-speed interconnect bottlenecks may also get stuck on the electrical chip. Still, without visible revenue elasticity, I do not buy the "AI networking beneficiary" label. Only when DSPs, switch chips, custom ASICs, and customer projects actually map to revenue do I count this layer as a bottleneck.

Splitting Packaging into Two Layers

The material splits packaging into two layers:

• First-level packaging: packaging bare optical dies and passive optical components into a TOSA, ROSA, or optical engine. Barriers are higher here, giving an edge to vendors with optical chip and component capabilities.
• Second-level packaging: integrating the optical engine with the DSP, PCB, thermal management, and form factor design into a pluggable module. More domestic and overseas vendors participate in module manufacturing and integration.

Even though both fall under the optical module umbrella, I evaluate these two layers separately. First-level packaging looks more like a core component and yield bottleneck, whereas second-level packaging looks more like integration, delivery, and customer lock-in. Because the profits of the two layers do not sit in the same place, I do not use one story to cover both sides.

CPO as an Architectural Migration

The core idea behind CPO is packaging the optical engine and electrical chip much closer together, shortening the electrical signal path to cut power consumption and latency while raising port density. The material mentions that CPO could reduce power consumption by 30%–50% and fits 1.6T and 3.2T interconnects.

This is an architectural migration rather than a new buzzword alone. Right now, CPO is still moving from labs and small-scale deployments toward mass production. I will not make calls based on who has a CPO angle; instead, I need to check four follow-up questions:

1. Which customers have already entered testing or procurement?
2. Which revenue lines will mass production change?
3. Will yield, thermal management, serviceability, and standardization slow down deployment?
4. Will pluggable modules stay mainstream for longer?

Four Questions to Verify

I check these four questions in order. As long as the news stays at the level of "AI needs more bandwidth" without specific procurement and revenue items, I apply a discount upfront.

Question	Evidence Needed to Verify	Links Where It Might Land
Has bandwidth demand entered procurement?	Cloud vendor capex, switch upgrades, 800G/1.6T shipments, customer guidance	Optical modules, DSPs, switch chips
Where is the actual choke point?	InP yield, DSP supply, packaging capacity, test cycle times, thermal management	Optical chips, DSPs, packaging, testing
Who keeps the profit?	AI data center revenue share, gross margin, customer concentration, contract duration	Across optical chips, DSPs, packaging, and module manufacturing
Has the market already priced it in?	Valuation levels, consensus expectations, order expectations	Determines whether an expectation gap still exists

Inside a cluster, HBM addresses memory bandwidth within and right next to the GPU, while optical interconnects handle cluster-scale data movement. The larger training and inference clusters get, the more likely bottlenecks are to spread from single-card compute to memory, networking, power, cooling, and packaging. Analyzing optical modules therefore cannot stop at the slogan "AI needs more bandwidth." You have to pin the news down to specific revenue lines and check 800G/1.6T module shipments, DSP ASPs, InP chip supply, CPO design-ins, and packaging yields. As for how memory price hikes can in turn force customers to change architectures, I wrote about that in Overpricing Bottlenecks Hurts AI CapEx.

Six Scenarios That Would Falsify the Thesis

If any one of the six scenarios below holds true, I will take the original bottleneck story down a notch.

1. Pluggable modules last longer. If CPO mass production and maintenance prove complex, pluggable optical modules may continue to dominate, and CPO-related revenue will arrive more slowly.
2. Demand is strong, but customers compress margins. Cloud vendors and switch vendors have strong bargaining power, so shipment growth does not necessarily lift gross margins.
3. Competition in assembly drives prices down. If competition in second-level packaging and module assembly is fierce, profit will trail revenue growth.
4. More profit stays with the electrical chips. When optical module shipments grow, more of the profit may flow to DSP and switch chip suppliers.
5. Expectations are already crowded. If the narrative around 800G, 1.6T, and CPO has already been priced in ahead of time, expectations could pull back on even a slight earnings miss.
6. Customers change the architecture. Higher integration, silicon photonics, CPO, or different cluster topologies could re-divide the value chain.

What Remains Unverified

I do not yet treat the following items as established facts:

• Shipment volumes, ASPs, and lead times for 800G and 1.6T optical modules.
• Disclosed AI data center revenue across optical chips, DSPs, packaging, and module manufacturing.
• Whether cloud vendors and switch vendors have explicitly mentioned deployments of 1.6T, CPO, or optical engine hardware.
• Customers, timelines, yields, and power consumption data for CPO moving from testing to mass production.
• Overseas customers, gross margins, and order visibility across each link of the domestic optical module supply chain.
• Whether market expectations have already priced in an optimistic outlook for the next two to three years.

I view optical modules as a chain of bottlenecks running from InP optical chips, DSPs, and optical packaging to CPO. Researching along this chain means identifying which link is hardest to expand capacity in, has the strongest pricing power, and is most likely to show up in financial statements within 1–4 quarters.

Reference

• *US-Listed Optical Transceiver Full Industry Chain Analysis* (*《美股光模块全产业链解析来了！》*): The details on InP optical chips, DSPs, first-level / second-level packaging, CPO potentially reducing power consumption by 30%–50%, and the speed upgrades from 400G to 3.2T all come from this supply chain material.